Present complementary metal oxide semiconductor (CMOS) dynamic random access memory (DRAM) circuits are frequently used for main memory in a variety of applications including laptop and notebook computer systems which are battery powered. These battery powered applications impose practical limitations such as speed, power, and feature size on dynamic random access memory design. Optimal performance of a system depends on an effective balance of these factors in the design.
The trend in dynamic random access memory design is to minimize power consumption, as operating frequency increases, by the reduction of capacitance and operating voltage. Reduction of circuit feature sizes effectively reduces the length of leads, the surface area of diffusions, and the space between diffusions. Shorter lead lengths and smaller diffused areas advantageously reduce circuit capacitance. Less space between diffused regions, however, may have the undesirable effect of creating parasitic leakage paths between adjacent diffusions due to a phenomenon known as the short channel effect. This phenomenon results in a reduction in the threshold voltage of parasitic field effect transistors formed between closely spaced diffused regions and in an increase in leakage current. One method of increasing the isolation or threshold voltage of the parasitic field effect transistors is to increase the bulk or substrate impurity surface concentration. Such an increase in the substrate impurity surface concentration is limited by the consequent undesirable increase in junction capacitance.
On-chip substrate bias generators for dynamic random access memories have become a standard practice in the industry because they reduce junction capacitance between diffused regions and the substrate. Typically a negative bias with respect to ground is applied to a P-type substrate by the on-chip substrate bias generator. This negative substrate bias V.sub.BB increases the reverse bias of all junctions formed between N-type diffusions and the P-type substrate. Junction capacitance decreases because it is inversely proportional to the square root of the reverse bias across the junction. For a dynamic random access memory, bitline junction capacitance is a major component of active power consumption that must be charged and discharged during active operation. This active power consumption is determined by the product of capacitance, the square of the operating voltage, and the operating frequency. Thus, a significant reduction in active power consumption is achieved because bitline junction capacitance dominates the total circuit capacitance of the dynamic random access memory.
A reduction in leakage current or improved isolation between closely spaced diffused regions is achieved by the application of negative bias V.sub.BB to a P-type substrate with respect to ground or reference supply V.sub.SS. The result of the negative bias is to increase the bulk to source potential of all N-channel transistors, including parasitic transistors, in common with the substrate. This increases the N-channel transistor threshold voltage by a phenomenon known as body effect, thereby decreasing leakage between the closely spaced diffused regions. Thus, the substrate bias V.sub.BB must be closely regulated over a variety of operating conditions, or large variations in speed and power of the dynamic random access memory will result from variations in N-channel transistor threshold voltage and junction capacitance.
Substrate bias regulation must comprehend large differences in substrate current during high-power active operation as well as low-power standby operation. In, U.S. Pat. No. 4,430,581, entitled SEMICONDUCTOR SUBSTRATE BIAS CIRCUIT, Jun-ichi Mogi et al use two substrate bias circuits. One of their bias circuits is always enabled and pumps substrate current at a constant frequency that is sufficient to compensate for junction leakage. The other bias circuit is enabled only during the active operation. It pumps substrate current at a frequency that is proportional to the dynamic random access memory operating frequency.
There are two notable issues with respect to the teaching of Mogi et al. First, the constant frequency bias circuit remains enabled when the variable frequency bias circuit is enabled. The variable frequency bias circuit is designed to operate in the dynamic random access memory active cycle and can pump much more current than the constant frequency bias circuit. Operating alone, the variable frequency bias circuit is sufficient to maintain a stable substrate bias level for current produced by both active operation and by junction leakage. Thus, the oscillator and pump circuit of the constant frequency bias circuit needlessly expend power during the active cycle. Second, the teaching of Mogi et al fails to satisfy some modes of operation which produce more substrate current than that which can be pumped by the active cycle bias circuit. Among these modes of operation are burn-in, where more substrate current is produced by high operating voltage, and parallel test, where more substrate current is produced by additional active arrays.